When designing large scale FET circuitry, the nominal load device dimensions for each circuit are selected such that a pre-defined maximum allowable power dissipation will not be exceeded despite variations in process parameters such as threshold voltage, transconductance, or topological variation. The minimum active device dimensions are selected such that the circuit exhibits acceptable voltage gain and noise immunity despite worse case of variations in these process parameters. Larger variations in these process parameters require the designer to specify larger active devices which in turn present increased loading to the circuits that drive them, thereby slowing delay propagation in the circuit. The circuit's worse case performance will be slower than the designed for, nominal performance by an amount that increases with the tolerance in the process and environmental parameters for the LSI chip.
Attempts have been made in the prior art to compensate for variations in process parameters on an LSI chip, an example of which is the Pleshko, et. al. U.S. Pat. No. 3,609,414, filed Aug. 20, 1968 and assigned to the instant assignee. Pleshko discloses an on-chip circuit for compensating for variations in the process parameters by compensating for the resulting threshold voltage variation in FET devices embodied in the chip, by controlling the substrate voltage of the chip. Although the Pleshko, et. al. invention works well for its particular application, it has the disadvantage of imposing the compensation voltage on every circuit on the chip, thereby precluding the selective compensation of multiple threshold circuits, such as enhance/deplete FET circuitry. An additional problem with the Pleshko, et. al. compensation technique is, that in an N-channel device compensated by substrate voltage control, high threshold voltages will be compensated by low substrate bias voltages. Low substrate bias voltages increase the junction capacitance which further degrades performance of the circuits. Also, low substrate bias voltages may increase the probability of undesirable parasitic FET action formed by surface inversion and low substrate bias.